1. Field of the Invention
The present invention relates generally to manufacturing of a semiconductor device. More specifically, the present invention provides a method and apparatus for forming a trench memory, such as dynamic random access memory (DRAM), with a monolithic conducting material.
2. Background Art
A trench memory, for example a dynamic random access memory (DRAM), is depicted, in cross-sectional view, in FIG. 1. As is typical the trench memory (e.g., DRAM) 1 has one capacitor 2 and one transistor 4 and further includes various constructs located within, or upon, a semiconductor substrate 6. Trench memory 1 includes capacitor 2, typically located within a trench 8, that is connected to a transistor (e.g., conventional MOSFET) 4 via a buried strap 10. Transistor 4 includes a gate conductor 12, gate dielectric 14, and a drain 16 and a source 18 on either side of gate conductor 12.
Lining a portion of trench 8 is a node dielectric 20. Above node dielectric 20, also lining a portion of trench 8 is an insulating collar 22 (or collar oxide). Also within trench 8 is conducting materials 24A, 24B, and 24C which conventionally are doped polysilicon (hereinafter “poly”). Located upon insulating collar 22 is a shallow trench isolation (STI) 26.
Due to the steps of constructing trench memory 1 and its various parts, trench 8 is filled by three (3) polysilicon materials (i.e., first poly 24A, second poly 24B, and third poly 24C). Because three poly materials 24A, 24B, 24C are placed within trench 8 at temporally distinct times, poly materials 24A, 24B, 24C are not monolithic. That is conducting materials 24A, 24B, 24C are not one, integrated piece of conducting material 24 in trench 8. First poly 24A is placed first. Second poly 24B is placed later, after placement of first poly 24A and intermittent steps. Third poly 24C is placed later, after placement of second poly 24B and other intermittent steps, as well.
Interfaces are created where each poly 24 abuts another adjoining poly 24. For example, a poly 24 to poly 24 interface is created where first poly 24A meets second poly 24B. Similarly, a second poly 24 to poly 24 interface is created where second poly 24B and third poly 24C meet. A shortcoming of this trench memory 1, and the method of making it, is that each interface increases the overall resistance of trench 8, thereby causing a concomitant reduction in the overall performance of trench memory 1. Further, there are several steps in placing first poly 24A, second poly 24B, and third poly 24C, thereby increasing process time and cost.
In view of the foregoing, there exists a need for an improved process for constructing trench memory that overcomes the aforementioned deficiencies.